Computer Organization and Architecture

Comprehensive Theory Notes for CBDT Assistant Director (Systems) Exam

1. Number Systems and Codes

Number System Conversions

From \ To	Decimal	Binary	Octal	Hexadecimal
Decimal	—	Repeated division by 2	Repeated division by 8	Repeated division by 16
Binary	Sum of powers of 2	—	Group by 3 bits (right to left)	Group by 4 bits (right to left)
Octal	Sum of powers of 8	Each digit → 3 bits	—	Via binary
Hexadecimal	Sum of powers of 16	Each digit → 4 bits	Via binary	—

Key Powers of 2

2^10 = 1024 (1 Kibi)
2^20 = 1,048,576 (1 Mebi)
2^30 = 1,073,741,824 (1 Gibi)
2^40 = 1,099,511,627,776 (1 Tebi)

Complements (for subtraction and negative numbers)

r's Complement (Radix Complement):
- Binary: 2's complement = 1's complement + 1
- Formula: 2^n - N (for n-bit number N)

(r-1)'s Complement (Diminished Radix Complement):
- Binary: 1's complement (flip all bits)
- Formula: (2^n - 1) - N

Signed Number Representations

Method	Range (n bits)	+0	-0
Sign-Magnitude	-(2^(n-1)-1) to +(2^(n-1)-1)	000...0	100...0
1's Complement	-(2^(n-1)-1) to +(2^(n-1)-1)	000...0	111...1
2's Complement	-2^(n-1) to +(2^(n-1)-1)	000...0	None (unique)

2's complement is the standard in modern computers because:
- Unique representation of zero
- Simple addition/subtraction circuitry
- Range is asymmetric (one more negative number)

Binary Codes

Code	Description	Example (Decimal 5)
BCD (8421)	Each decimal digit → 4-bit binary	0101
Excess-3	BCD + 3	1000
Gray Code	Adjacent values differ by 1 bit	0111
ASCII	7-bit character encoding	0100101 (53 in hex)

Gray Code Conversion (Binary → Gray):
- MSB remains same
- Each subsequent bit = XOR of current and previous binary bit

2. Boolean Algebra and Logic Gates

Basic Laws

Law	AND Form	OR Form
Commutative	A·B = B·A	A+B = B+A
Associative	A·(B·C) = (A·B)·C	A+(B+C) = (A+B)+C
Distributive	A·(B+C) = A·B+A·C	A+(B·C) = (A+B)·(A+C)
Identity	A·1 = A	A+0 = A
Complement	A·A' = 0	A+A' = 1
Idempotent	A·A = A	A+A = A
Absorption	A·(A+B) = A	A+(A·B) = A
De Morgan's	(A·B)' = A'+B'	(A+B)' = A'·B'

De Morgan's Theorems (Very Important)

(A · B)' = A' + B' — Complement of AND = OR of complements
(A + B)' = A' · B' — Complement of OR = AND of complements

Universal Gates

NAND and NOR are universal gates (can implement any Boolean function)
Any logic circuit can be built using only NAND gates or only NOR gates

Standard Forms

Sum of Products (SOP): AND terms ORed together
Product of Sums (POS): OR terms ANDed together

Minterm: Product term containing all variables (used in SOP)
Maxterm: Sum term containing all variables (used in POS)

Karnaugh Map (K-Map) Simplification

2-variable K-Map: 4 cells
3-variable K-Map: 8 cells
4-variable K-Map: 16 cells
5-variable K-Map: 32 cells (two 4-variable maps)

Grouping rules:
- Groups must be rectangular
- Group size must be power of 2 (1, 2, 4, 8, 16...)
- Groups can wrap around edges
- Overlapping groups are allowed
- Don't cares (X) can be included in groups

3. Combinational Circuits

Half Adder

Adds two single-bit numbers
Sum = A ⊕ B (XOR)
Carry = A · B (AND)

Full Adder

Adds three bits (A, B, Cin)
Sum = A ⊕ B ⊕ Cin
Carry = A·B + Cin·(A ⊕ B)

Multiplexer (MUX)

2^n inputs, 1 output, n select lines
Selects one of many inputs based on select lines
Applications: Parallel-to-serial conversion, function generator, data routing

Demultiplexer (DEMUX)

1 input, 2^n outputs, n select lines
Routes single input to one of many outputs
Applications: Serial-to-parallel conversion, data distribution

Decoder

n inputs, 2^n outputs
Activates one of 2^n outputs based on input combination
Applications: Memory address decoding, instruction decoding

Encoder

2^n inputs, n outputs
Opposite of decoder; encodes input into binary code
Priority encoder: Handles multiple active inputs by priority

Comparator

Compares two binary numbers
Outputs: A > B, A < B, A = B

Arithmetic Logic Unit (ALU)

Performs arithmetic (add, subtract, increment, decrement) and logical (AND, OR, NOT, XOR) operations
Key building block of the CPU

4. Sequential Circuits

Flip-Flops

Flip-Flop	Characteristic Equation	Excitation (Q→Q+1)
SR	Q(t+1) = S + R'·Q (SR=0)	S=1, R=0
JK	Q(t+1) = J·Q' + K'·Q	J=1, K=0
D	Q(t+1) = D	D=1
T	Q(t+1) = T ⊕ Q	T=1

JK Flip-Flop is the most versatile (no invalid state; can emulate SR, D, and T)

Flip-Flop Conversions

From → To	Method
SR → JK	S = J·Q', R = K·Q
SR → D	S = D, R = D'
JK → D	J = D, K = D'
JK → T	J = T, K = T
D → T	D = T ⊕ Q

Registers

Shift Register: Shifts data left/right
SISO (Serial In Serial Out)
SIPO (Serial In Parallel Out)
PISO (Parallel In Serial Out)
PIPO (Parallel In Parallel Out)
Universal Register: Can shift left, right, and load parallel

Counters

Asynchronous (Ripple) Counter:
- Output of one flip-flop drives clock of next
- Simple but slow (propagation delay accumulates)
- n flip-flops → 2^n states

Synchronous Counter:
- All flip-flops share the same clock
- Faster, no ripple delay
- More complex wiring

Common Counter Types:
| Type | Description |
|------|-------------|
| Ring Counter | Circular shift register; n states with n flip-flops |
| Johnson Counter | Twisted ring; 2n states with n flip-flops |
| Mod-N Counter | Counts from 0 to N-1, then resets |
| Up/Down Counter | Can count in both directions |

Counters for exam:
- n-bit binary counter: counts 0 to 2^n - 1
- Mod-10 (Decade) counter: counts 0 to 9
- Ring counter: only one flip-flop is 1 at a time
- Johnson counter: 2n unique states

5. CPU Architecture

Basic CPU Components

CPU
├── ALU (Arithmetic Logic Unit)
│   ├── Arithmetic operations (+, -, ×, ÷)
│   └── Logical operations (AND, OR, NOT, XOR)
├── Control Unit
│   ├── Instruction decoding
│   └── Control signal generation
├── Registers
│   ├── General Purpose (R0-R7, etc.)
│   ├── Special Purpose
│   │   ├── PC (Program Counter)
│   │   ├── IR (Instruction Register)
│   │   ├── MAR (Memory Address Register)
│   │   ├── MBR/MDR (Memory Buffer/Data Register)
│   │   ├── ACC (Accumulator)
│   │   └── Flag/Status Register
│   └── Stack Pointer (SP)
└── Internal Buses

Instruction Cycle

1. Fetch: MAR ← [PC]
          MBR ← Memory[MAR]
          IR ← MBR
          PC ← PC + 1
2. Decode: Decode IR
3. Execute: Perform operation
4. (Optional) Store: Write results

Instruction Format

┌──────────────┬─────────────┬──────────────┐
│  Opcode      │  Operand 1  │  Operand 2   │
│  (operation) │  (address)  │  (address)   │
└──────────────┴─────────────┴──────────────┘

Types of Instructions

Data Transfer: LOAD, STORE, MOVE, PUSH, POP
Arithmetic: ADD, SUB, MUL, DIV, INC, DEC
Logical: AND, OR, NOT, XOR, SHIFT, ROTATE
Control: JMP, CALL, RET, JZ, JNZ, JC, JNC
I/O: IN, OUT

Instruction Types by Operands

Type	Example	Operands in instruction
Zero-address	PUSH, POP	Stack-based (implicit)
One-address	LOAD A, ADD A	One explicit operand
Two-address	MOV A, B	Two operands
Three-address	ADD A, B, C	Three operands

6. Addressing Modes

Mode	Description	Effective Address	Example
Immediate	Operand is in instruction	N/A	MOV R1, #5
Direct	Address field = effective address	EA = A	MOV R1, [2000]
Indirect	Address field points to address of operand	EA = (A)	MOV R1, [[2000]]
Register	Operand is in register	Register	MOV R1, R2
Register Indirect	Register holds address	EA = (R)	MOV R1, (R2)
Indexed	EA = Index register + offset	EA = IX + A	MOV R1, 10(IX)
Base Register	EA = Base register + offset	EA = BR + A	MOV R1, 5(BR)
Relative	EA = PC + offset	EA = PC + A	JMP +20
Auto-increment	EA = (R), then R++	EA = (R), R = R+1	MOV (R1)+, R2
Auto-decrement	R--, then EA = (R)	R = R-1, EA = (R)	MOV R1, -(R2)

Key Points:
- Immediate: Fastest (no memory access for operand)
- Indirect: Slowest (two memory accesses)
- Relative addressing supports relocatable code
- Base register addressing supports segmentation

7. Instruction Pipelining

Pipelining divides instruction execution into stages, allowing multiple instructions to be processed simultaneously.

Classic 5-Stage Pipeline (RISC)

IF → ID → EX → MEM → WB

IF (Instruction Fetch): Fetch instruction from memory
ID (Instruction Decode): Decode and read registers
EX (Execute): ALU operation
MEM (Memory Access): Data memory access
WB (Write Back): Write result to register

Speedup

Ideal Speedup = k (where k = number of stages)

Actual Speedup = (n × k) / (k + n - 1) where n = number of instructions

Throughput = Number of instructions / Total time

Pipeline Hazards

Type	Cause	Solution
Structural	Resource conflict	Duplicate resources, pipeline stalls
Data	Data dependency	Forwarding/bypassing, stalling
Control	Branch instructions	Branch prediction, delayed branching

Data Hazards:
- RAW (Read After Write): Most common; instruction needs result of previous
- WAR (Write After Read): Out-of-order execution issue
- WAW (Write After Write): Out-of-order execution issue

Solutions:
- Data forwarding: Route result directly to next instruction
- Stalling (bubbles): Insert NOPs
- Compiler scheduling: Reorder instructions

Branch Penalty: Cycles wasted when branch is taken
- Branch prediction: Predict taken/not-taken
- Delayed branch: Execute instruction after branch regardless
- BTB (Branch Target Buffer): Cache of branch targets

8. Memory Hierarchy

CPU Registers  ←── Fastest, Smallest, Most Expensive
    ↓
Cache (L1, L2, L3)
    ↓
Main Memory (RAM)
    ↓
Secondary Storage (HDD/SSD)
    ↓
Tertiary Storage (Tape)  ←── Slowest, Largest, Cheapest

Memory Parameters Comparison

Memory Type	Access Time	Cost/Bit	Volatility
Registers	< 1 ns	Highest	Volatile
L1 Cache	1-2 ns	Very High	Volatile
L2 Cache	3-10 ns	High	Volatile
L3 Cache	10-30 ns	Moderate	Volatile
RAM (DRAM)	50-100 ns	Moderate	Volatile
SSD	25-100 μs	Low	Non-volatile
HDD	5-10 ms	Very Low	Non-volatile

Cache Memory

Cache hit: Data found in cache
Cache miss: Data not in cache; must fetch from main memory

Hit Ratio (h): Fraction of accesses that are hits
Miss Ratio: 1 - h

Average Access Time = h × Tc + (1-h) × Tm
Where Tc = cache access time, Tm = main memory access time

Effective Access Time (EAT) = h × Tc + (1-h) × (Tc + Tm) (with simultaneous access: EAT = h × Tc + (1-h) × Tm)

Cache Mapping Techniques

1. Direct Mapping

Each block of main memory maps to exactly one cache line
Cache line = (Block address) mod (Number of cache lines)
Advantage: Simple, fast
Disadvantage: High conflict misses

2. Fully Associative Mapping

Any block can go in any cache line
Advantage: Fewest misses
Disadvantage: Complex hardware (comparators for all lines)

3. Set-Associative Mapping

Cache divided into sets; each set has multiple lines (ways)
Block maps to a specific set, but can occupy any line within that set
Set = (Block address) mod (Number of sets)
2-way, 4-way, 8-way are common
Compromise between direct and fully associative

Cache Replacement Policies

Policy	Description
LRU (Least Recently Used)	Replace block not used for longest time
FIFO	Replace oldest block
Random	Replace random block
LFU (Least Frequently Used)	Replace least frequently accessed

Cache Write Policies

Policy	Description
Write-through	Write to both cache and main memory simultaneously
Write-back	Write only to cache; memory updated when block is replaced
Write-allocate	On write miss, load block into cache first
No-write-allocate	On write miss, write directly to memory

Locality of Reference

Temporal Locality: Recently accessed items likely to be accessed again
Spatial Locality: Nearby addresses likely to be accessed soon

9. Virtual Memory

Virtual memory allows programs to use more memory than physically available by using disk as an extension of RAM.

Paging

Divides virtual address space into fixed-size pages
Physical memory divided into frames of same size
Page table maps virtual pages to physical frames
Page size: Typically 4 KB (can be 2 MB, 1 GB for huge pages)

Address Translation:

Virtual Address = [Page Number | Offset]
Physical Address = [Frame Number | Offset]

Page Fault: When referenced page is not in physical memory
- OS loads page from disk
- May need to replace an existing page

Page Replacement Algorithms

Algorithm	Description	Performance
FIFO	Replace oldest page	Poor (Belady's anomaly)
LRU	Replace least recently used	Good (stack algorithm)
Optimal (OPT)	Replace page not used for longest future	Theoretical best
Second Chance (Clock)	FIFO with reference bit	Practical approximation of LRU
LFU	Replace least frequently used	Moderate

Belady's Anomaly: In FIFO, increasing page frames can increase page faults!

Segmentation

Divides program into logical segments (code, data, stack, heap)
Variable-sized blocks
Segment table contains base address and limit for each segment
Can cause external fragmentation

Segmented Paging

Combines segmentation and paging
Each segment is divided into pages
Eliminates external fragmentation while maintaining logical structure

TLB (Translation Lookaside Buffer)

Cache for page table entries
TLB hit: Fast address translation (no memory access for page table)
TLB miss: Access page table in memory
Effective access time = (h × Ttlb) + (1-h) × (Ttlb + Tmem)

10. I/O Organization

I/O Techniques

Technique	Description	CPU Involvement
Programmed I/O	CPU polls I/O device status	High (busy waiting)
Interrupt-driven I/O	Device interrupts CPU when ready	Medium
DMA (Direct Memory Access)	DMA controller transfers data directly	Low (CPU only initiates)
Channel I/O	Dedicated I/O processor	Minimal

DMA (Direct Memory Access)

CPU initiates DMA transfer (sets address, count)
DMA controller requests bus (HOLD signal)
CPU grants bus (HLDA signal)
DMA controller transfers data directly between device and memory
DMA controller interrupts CPU when complete

DMA Transfer Modes:
- Burst mode: Transfers entire block at once (CPU blocked during transfer)
- Cycle stealing: Transfers one word at a time (CPU gets bus between transfers)
- Transparent: Transfers only when CPU isn't using bus

Interrupts

Types of Interrupts:
| Type | Source | Example |
|------|--------|---------|
| Hardware | External device | Keyboard, timer, disk |
| Software (Trap) | Program instruction | System call, divide by zero |
| Internal | CPU error | Overflow, illegal instruction |

Interrupt Handling Process:
1. CPU finishes current instruction
2. Save context (push registers to stack)
3. Identify interrupt source (vectored/non-vectored)
4. Jump to Interrupt Service Routine (ISR)
5. Execute ISR
6. Restore context
7. Resume interrupted program

Interrupt Priority: Multiple interrupts handled by priority (hardware or software)

11. RISC vs CISC

Feature	RISC	CISC
Instruction Set	Small, simple	Large, complex
Instruction Length	Fixed	Variable
Execution Time	Most execute in 1 cycle	Multiple cycles
Addressing Modes	Few (3-5)	Many (12-24)
Registers	Many (32+)	Few (8-16)
Pipelining	Easy to pipeline	Difficult
Code Size	Larger (more instructions)	Smaller (fewer instructions)
Memory Access	Load/Store only	Any instruction can access memory
Control Unit	Hardwired	Microprogrammed
Examples	ARM, MIPS, SPARC, RISC-V	x86, VAX, 8086

Modern trend: x86 (CISC) internally translates to RISC-like micro-operations

12. ALU Design

ALU Operations

Arithmetic: Add, Subtract, Increment, Decrement, Multiply, Divide
Logical: AND, OR, NOT, XOR, NAND, NOR
Shift: Logical shift left/right, Arithmetic shift left/right, Rotate

1-Bit ALU

Takes two 1-bit inputs (A, B)
Control lines select operation
Outputs result and carry

n-Bit ALU

Built from n 1-bit ALUs
Ripple carry: Carry propagates through all bits (slow)
Carry lookahead: Computes carry in parallel (fast, complex)

Carry Lookahead Adder (CLA):
- Generate (G): G = A · B (carry generated)
- Propagate (P): P = A ⊕ B (carry propagated)
- Carry out: C_out = G + P · C_in
- Eliminates carry propagation delay

13. Microprogrammed Control

Hardwired vs Microprogrammed Control

Feature	Hardwired	Microprogrammed
Speed	Faster	Slower
Flexibility	Difficult to modify	Easy to modify
Complexity	Complex for large ISAs	Simpler for large ISAs
Cost	Higher for complex CPUs	Lower for complex CPUs
Used in	RISC processors	CISC processors

Microinstruction Format

┌──────────────┬──────────────┬──────────────┐
│  Control     │  Next Addr   │  Condition   │
│  Signals     │  Field       │  Field       │
└──────────────┴──────────────┴──────────────┘

Horizontal vs Vertical Microcode

Type	Description
Horizontal	Wide microinstruction; many control signals; parallel; fast
Vertical	Narrow microinstruction; encoded; sequential; compact

14. Key Formulas

CPU Execution Time: T = IC × CPI × T_clock
IC = Instruction Count, CPI = Cycles Per Instruction, T_clock = Clock cycle time
MIPS (Million Instructions Per Second): MIPS = IC / (Execution Time × 10^6) = Clock Rate / (CPI × 10^6)
Speedup: Speedup = Execution Time_old / Execution Time_new
Amdahl's Law: Speedup = 1 / ((1 - f) + f/s)
f = fraction improved, s = speedup of improved portion
Cache Performance: EAT = Hit Time + (Miss Rate × Miss Penalty)
CPU Utilization: CPU Utilization = 1 - (Idle Time / Total Time)
Throughput: Throughput = Number of instructions / Total execution time
Pipeline Speedup: S = (n × k) / (k + n - 1)
Effective Memory Access: EMAT = h × Tc + (1-h) × (Tc + Tm)
Bandwidth: Bandwidth = Data transferred / Time taken

15. Exam Tips

2's complement is the standard signed number representation
De Morgan's theorems are frequently tested
K-Map grouping rules must be memorized
Pipeline hazards: Structural, Data, Control — know all three
Cache mapping: Direct vs Associative vs Set-Associative
Belady's Anomaly occurs in FIFO page replacement
DMA frees CPU from I/O data transfer
RISC: Load/Store architecture, fixed-length, hardwired control
CISC: Complex instructions, variable-length, microprogrammed control
Amdahl's Law is important for performance improvement questions
TLB is a cache for page table entries
Effective Access Time formula is frequently asked

Practice Questions

10 MCQs for Computer Organization and Architecture with detailed explanations.

Q1. Consider the following about | — | Repeated division by 2 | Repeated division by 8 | Repe...

A. It requires a minimum of O(n²) time complexity
B. It is not applicable in distributed systems
C. | — | Repeated division by 2 | Repeated division by 8 | Repeated division by 16 |
|
D. It applies only to sequential processing models

✅ Correct Answer: Option C

This is a standard concept in Computer Organization and Architecture. The answer follows from the fundamental definitions and properties covered in this topic.

Why other options are incorrect:
- Option A (It requires a minimum of O(n²) time complexity...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.
- Option B (It is not applicable in distributed systems...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.
- Option D (It applies only to sequential processing models...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.

Q2. Consider the following about (r-1)'s Complement (Diminished Radix Complement):...

A. (r-1)'s Complement (Diminished Radix Complement):
B. It requires a minimum of O(n²) time complexity
C. It is not applicable in distributed systems
D. It applies only to sequential processing models

✅ Correct Answer: Option A

Explanation:
The correct answer is Option A — (r-1)'s Complement (Diminished Radix Complement):.

This is a standard concept in Computer Organization and Architecture. The answer follows from the fundamental definitions and properties covered in this topic.

Why other options are incorrect:
- Option B (It requires a minimum of O(n²) time complexity...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.
- Option C (It is not applicable in distributed systems...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.
- Option D (It applies only to sequential processing models...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.

Q3. Which of the following best describes 2's complement?

A. | — | Repeated division by 2 | Repeated division by 8 | Repeated division by 16 |
|
B. the standard
C. (r-1)'s Complement (Diminished Radix Complement):
D. are universal gates (can implement any Boolean function)
Any logic circuit can be built using only

✅ Correct Answer: Option B

Explanation:
The correct answer is Option B — the standard.

This is a standard concept in Computer Organization and Architecture. The answer follows from the fundamental definitions and properties covered in this topic.

Why other options are incorrect:
- Option A (| — | Repeated division by 2 | Repeated division by 8 | Repeated division by 16 ...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.
- Option C ((r-1)'s Complement (Diminished Radix Complement):...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.
- Option D (are universal gates (can implement any Boolean function)
- Any logic circuit can...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.

Q4. Consider the following about are universal gates (can implement any Boolean function)

A...
A. It requires a minimum of O(n²) time complexity
B. It applies only to sequential processing models
C. It is not applicable in distributed systems
D. are universal gates (can implement any Boolean function)
Any logic circuit can be built using only NAND gates or only

✅ Correct Answer: Option D

Explanation:
The correct answer is Option D — are universal gates (can implement any Boolean function)
- Any logic circuit can be built using only NAND gates or only .

This is a standard concept in Computer Organization and Architecture. The answer follows from the fundamental definitions and properties covered in this topic.

Why other options are incorrect:
- Option A (It requires a minimum of O(n²) time complexity...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.
- Option B (It applies only to sequential processing models...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.
- Option C (It is not applicable in distributed systems...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.

Q5. Consider the following about None (unique) |

2's complement is the standard in moder...

A. None (unique) |

2's complement is the standard in modern computers because:
- Unique representation of zero
- Simpl
- B. It requires a minimum of O(n²) time complexity
- C. It applies only to sequential processing models
- D. It is not applicable in distributed systems

✅ Correct Answer: Option A

Explanation:
The correct answer is Option A — None (unique) |

2's complement is the standard in modern computers because:
- Unique representation of zero
- Simpl.

This is a standard concept in Computer Organization and Architecture. The answer follows from the fundamental definitions and properties covered in this topic.

Why other options are incorrect:
- Option B (It requires a minimum of O(n²) time complexity...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.
- Option C (It applies only to sequential processing models...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.
- Option D (It is not applicable in distributed systems...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.

Q6. Consider the following about Binary: 2's complement = 1's complement + 1...

A. It requires a minimum of O(n²) time complexity
B. Binary: 2's complement = 1's complement + 1
C. It applies only to sequential processing models
D. It is not applicable in distributed systems

✅ Correct Answer: Option B

Explanation:
The correct answer is Option B — Binary: 2's complement = 1's complement + 1.

This is a standard concept in Computer Organization and Architecture. The answer follows from the fundamental definitions and properties covered in this topic.

Why other options are incorrect:
- Option A (It requires a minimum of O(n²) time complexity...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.
- Option C (It applies only to sequential processing models...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.
- Option D (It is not applicable in distributed systems...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.

Q7. Consider the following about Formula: 2^n - N (for n-bit number N)...

A. It applies only to sequential processing models
B. Formula: 2^n - N (for n-bit number N)
C. It requires a minimum of O(n²) time complexity
D. It is not applicable in distributed systems

✅ Correct Answer: Option B

Explanation:
The correct answer is Option B — Formula: 2^n - N (for n-bit number N).

This is a standard concept in Computer Organization and Architecture. The answer follows from the fundamental definitions and properties covered in this topic.

Why other options are incorrect:
- Option A (It applies only to sequential processing models...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.
- Option C (It requires a minimum of O(n²) time complexity...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.
- Option D (It is not applicable in distributed systems...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.

Q8. Consider the following about Binary: 1's complement (flip all bits)...

A. It applies only to sequential processing models
B. It is not applicable in distributed systems
C. It requires a minimum of O(n²) time complexity
D. Binary: 1's complement (flip all bits)

✅ Correct Answer: Option D

Explanation:
The correct answer is Option D — Binary: 1's complement (flip all bits).

This is a standard concept in Computer Organization and Architecture. The answer follows from the fundamental definitions and properties covered in this topic.

Why other options are incorrect:
- Option A (It applies only to sequential processing models...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.
- Option B (It is not applicable in distributed systems...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.
- Option C (It requires a minimum of O(n²) time complexity...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.

Q9. Consider the following about Formula: (2^n - 1) - N...

A. It is not applicable in distributed systems
B. It applies only to sequential processing models
C. Formula: (2^n - 1) - N
D. It requires a minimum of O(n²) time complexity

✅ Correct Answer: Option C

Explanation:
The correct answer is Option C — Formula: (2^n - 1) - N.

This is a standard concept in Computer Organization and Architecture. The answer follows from the fundamental definitions and properties covered in this topic.

Why other options are incorrect:
- Option A (It is not applicable in distributed systems...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.
- Option B (It applies only to sequential processing models...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.
- Option D (It requires a minimum of O(n²) time complexity...) — This does not correctly answer the question as it either misstates the concept or refers to a different context.

Q10. Consider the following about in modern computers because:

Unique representation of zero...
A. It requires a minimum of O(n²) time complexity
B. It is not applicable in distributed systems
C. in modern computers because:
Unique representation of zero
D. It applies only to sequential processing models

✅ Correct Answer: Option C

Explanation:
The correct answer is Option C — in modern computers because:
- Unique representation of zero.

This is a standard concept in Computer Organization and Architecture. The answer follows from the fundamental definitions and properties covered in this topic.